In radio frequency or wireless communication systems, a radio frequency (RF) receiver is a fundamental building block. The zero- and low-IF receiver (RX) architectures dominate today's low-cost wireless receiver market. For such receivers, the wanted signal is down-converted to DC, or close to DC, by the RX mixer. Before this mixer, the only frequency selectivity provided is, typically, band selectivity via the duplexer or the RX (surface-acoustic wave, SAW) filter (for frequency-division duplex, FDD, or time-division duplex, TDD, systems, respectively). In the RX-band adjacent-channel signals and leakage from the terminal's own transmitter (TX) may be much stronger than the wanted signal.
These off-channel signals are typically suppressed by the channel-select filters (CSF) following the RX mixer. Up to the CSF all circuitry has to support the full dynamic range (DR) of the wanted signal and all off-channel signals, including sufficient margin to the noise and interference floor required for proper signal detection, present at the LNA input. For the low-noise amplifier (LNA) the floor is determined by the thermal noise of its input signal, and the maximum signal is limited by the supply voltage and its bias current. For subsequent stages the signal power is increased, and for power-consumption reasons this means some voltage gain (say 30 dB) is applied stressing the upper limit of the dynamic range as the supply voltage is (about) the same for all the circuitry.
To relax the dynamic-range requirements in later stages, channel-select filtering is applied and ideally (with brick-wall filters) this would result in only the wanted signal challenging the upper limit of the dynamic range after the CSF. Today's receivers typically implement the CSF as a passive pole at the mixer output followed by an active ladder, or biquad-based, low-pass filter resulting in a finite attenuation of the off-channel signals. To keep the thermal noise low, the filter capacitors have to be relatively large (the available thermal noise voltage vn across a capacitor C is vn2=kT/C, where k is Boltzmann's constant and T is the absolute temperature) and they add significantly to the circuit area, and hence cost. These capacitors also add to the power consumption as a high bias current is required to drive them without generating too much distortion (which results in inter-modulation noise). In a multi-standard (e.g. GSM, WCDMA and LTE) receiver the CSF response has to be optimized for each mode, either by shifting the filter poles or by switching between fixed frequency filters, otherwise adjacent-channel suppression will be effective only for the mode with the widest bandwidth.
After the CSF the resulting signal is digitized in an analog-to-digital converter (ADC). Because the analog CSF has limited off-channel suppression, for component tolerance and signal integrity reasons, the maximum level of the signal out of the CSF will be set by a strong off-channel signal or TX leakage. Thus, the ADC has to have a higher dynamic range than what is required by the wanted signal alone. In practice this is accomplished by letting the wanted signal stay well below the ADC clipping level (except perhaps for the case when the wanted signal is approaching its maximum signal level in which case it is at least as strong as the off channel and no extra dynamic range margin is needed). This extra dynamic range increases the complexity, size, and power consumption of the ADC. The clipping point is close to the compression point (CPi and CPO for input- and output-referred compression, respectively) which is a more convenient way to measure the maximum signal level. The CPi (CPO) is defined as the input (output) signal level where the gain drops by 1 dB from its small-signal value.
The ADC noise floor for the wanted signal (i.e. the on-channel noise floor) is typically similar to, or lower than, the corresponding noise floor at the CSF output. ADC off-channel noise can often be ignored as it is usually not limiting the design and it can advantageously be filtered out by subsequent digital filters.
A very popular ADC topology is the Delta-Sigma ADC. In this topology, the input signal is fed through a filter (e.g. a set of integrators) in front of a quantizer. The quantizer output is routed to a digital-to-analog converter (DAC) who's output is subtracted from the input signal at the ADC input forming a feedback loop.
To increase RX integration it is desirable to combine the ADC and channel-select filters such that (some) filter integrators also may contribute in suppressing the ADC noise. Further, for multi-standard receivers it is desirable to move most of the selectivity into the digital domain where a flexible and tighter filter response can be accomplished, and an ADC with a compression point that increases with the frequency offset would enable more filtering in the digital domain. Thus, a low on-channel noise floor and high off-channel compression point are desirable features of an ADC.
In WO 2012/073117 it has been suggested that the noise contribution of the ADC can be reduced by making it a part of the CSF. They suggest to replace the feedback resistor in a low-pass Rauch filter by an ADC-DAC cascade. By feeding the ADC symbols to a feedback DAC with the proper transfer gain, which replaces the feedback resistor, the filter behavior is preserved, except for the fact that the ADC noise now occurs inside the filter feedback loop and the filter integrator gain helps suppressing this noise. The noise shaping now has a zero at the origin causing the improvement to depend on the (normalized) filter bandwidth. Thus, the input-referred noise of a wide CSF contains less ADC noise than a CSF with a cut-off at the channel bandwidth. Thus, to fully exploit the ADC noise suppression, the CSF bandwidth needs to be wide causing poor attenuation for adjacent channels.
In summary, the circuit of that document has replaced a resistor in the Rauch low-pass CSF with an ADC-DAC cascade and accomplished a filtering ADC. This merged CSF and ADC yields an additional single zero in the ADC noise shaping reducing the input-referred on-channel ADC noise contribution. The analog-to-digital converter can be e.g. a Delta-Sigma converter. In the document it has also been shown that higher-order noise shaping can be accomplished by increasing the order of the Delta-Sigma modulator in the ADC itself. This is, however, equivalent to improving a stand-alone ADC and does not take any benefit from the CSF. Any integrators added to the Delta-Sigma modulator do not contribute to the CSF and will, thus, just add to the circuit area (cost), power consumption and aggravate any ADC modulator stability issues.
Although useful improvements are demonstrated in WO 2012/073117, the additional noise shaping provided by the CSF is only of first order, and there is a conflict with CSF and the signal bandwidth and, thus, there is a need for further improvements.